In one aspect, the inventions relate to a semiconductor memory cell, array, and device, and techniques for improving, enhancing and/or controlling variations of operating and/or response parameter(s) or characteristic(s) of the memory cell, array and/or device; and more particularly, in one aspect, to improving, enhancing and/or controlling variations of such parameter(s) or characteristic(s) of the semiconductor dynamic random access memory (“DRAM”) cell, array and/or device wherein the memory cell(s) includes an electrically floating body in which an electrical charge is stored.
Briefly, there is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials and devices that improve performance, reduce leakage current and enhance overall scaling. However, scaling down of transistor sizes often leads to increase of variations of the operating and/or response characteristics. These variations or mismatch tend to have a significant impact on precision integrated circuit (“IC”) design. Indeed, due to variations or mismatch, IC designers, such as DRAM designers, typically include substantial design margin or risk yield loss, both of which adversely affect speed, efficiency and production costs.
One type of dynamic random access memory cell is based on, among other things, a floating body effect of Silicon-on-Insulator (“SOI”) transistors. (See, for example, U.S. patent application Ser. No. 10/450,238, Fazan et al., filed Jun. 10, 2003 and entitled “Semiconductor Device”, hereinafter “Semiconductor Memory Device Patent Application”). In this regard, the memory cell may consist of a PD or a FD SOI transistor (or transistor formed in bulk material/substrate) on having a channel, which is disposed adjacent to the body and separated therefrom by a gate dielectric. The body region of the transistor is electrically floating in view of the insulation or non-conductive region (for example, in bulk-type material/substrate) disposed beneath the body region. The state of memory cell is determined by the concentration of charge within the body region of the SOI transistor.
Such an electrically floating body memory cell has at least two current states corresponding to different logic states, for example, a logic high or State “1” and a logic low or State “0”. With reference to FIGS. 1A, 1B and 1C, in one embodiment, semiconductor DRAM device 10 includes a plurality of memory cells 12, arranged in an array 10a, wherein each memory cell 12 includes transistor 14 having gate 16, body region 18, which is electrically floating, source region 20 and drain region 22. The body region 18 is disposed between source region 20 and drain region 22. Moreover, body region 18 is disposed on or above region 24, which may be an insulation region (for example, in SOI material/substrate) or non-conductive region (for example, in bulk-type material). The insulation or non-conductive region is disposed on substrate 26.
Notably, the entire contents of the Semiconductor Memory Device Patent Application, including, for example, the features, attributes, architectures, configurations, materials, techniques and advantages described and illustrated therein, are incorporated by reference herein. SOI is a material in which such devices may be fabricated on or in (hereinafter collectively “on”). Such devices are known as SOI devices and include, for example, partially depleted (PD), fully depleted (FD) devices, multiple gate devices (for example, double or triple gate), and Fin-FET. SOI devices have demonstrated improved performance (for example, speed), reduced leakage current characteristics and considerable enhancement in scaling.
Data is written into or read from a selected memory cell by applying suitable control signals to a selected word line(s) 28, a selected source line(s) 30 and/or a selected bit line(s) 32. In response, charge carriers are accumulated in or emitted and/or ejected from electrically floating body region 18 wherein the data states are defined by the amount of carriers within electrically floating body region 18. As mentioned above, memory cell 12 of DRAM array 10 operates by accumulating majority carriers (electrons or holes) 34 in, or emitting/ejecting majority carriers 34 from body region 18 of, for example, N-channel transistors. (See, FIGS. 2A and 2B). In this regard, accumulating majority carriers (in this example, “holes”) 34 in body region 18 of memory cells 12 via, for example, impact ionization near source region 20 and/or drain region 22, is representative of a logic high or State “1”. (See, FIG. 2A). Emitting or ejecting majority carriers 30 from body region 18 via, for example, forward biasing the source/body junction and/or the drain/body junction, is representative of a logic low or State “0”. (See, FIG. 2B).
Reading is performed by comparison of a cell current with the current from a reference cell that is usually placed between the State “1” and State “0”. Several techniques may be implemented to read the data stored in (or write the data into) memory cells 12 of DRAM device 10. For example, a current sense amplifier (not illustrated) may be employed to read the data stored in memory cells 12. In this regard, a current sense amplifier may compare the cell current to a reference current, for example, the current of a reference cell (not illustrated). From that comparison, it may be determined whether memory cell 12 contained a logic high (relatively more majority carries 34 contained within body region 18) or logic low data state (relatively less majority carries 28 contained within body region 18).
For at least the purposes of this discussion, logic high or State “1” corresponds to an increased concentration of majority carries in the body region relative to a non-programmed device and/or a device that is programmed with a logic low or State “0”. In contrast, logic low or State “0” corresponds to a reduced concentration of majority carries in the body region relative to a non-programmed device and/or a device that is programmed with a logic high or State “1 ”.
A sufficiently large statistical variation in the device characteristics (for example, device currents) may cause or lead to an erroneous reading of the data state stored in the device. (See, FIG. 3). In contrast, a narrow statistical variation in the device characteristics tends to enhance uniformity of operation and performance of the devices. This provides greater confidence that the data stored in the memory device is correctly read during a read operation.
While electrically floating body transistors of memory cells (for example, SOI transistors) are highly scalable, variations or mismatch of transistor characteristics result in IC designers incorporating significant design margin to enhance or maximize yield. There is a need for ICs (for example, ICs that include electrically floating body transistors of memory cells) that incorporate circuitry and/or techniques that address variations or mismatch of transistor characteristics. In this way, IC designers may eliminate the need for substantial design margin or risk yield loss, which may adversely affect speed, efficiency and production costs.